Software Profiling to Improve Network on Chip Performance

Network on chip (NoC) processors utilize network connections in place of traditional bus or cross bar interconnects in order to improve performance, power consumption, and scalability in modern multicore processors. However, superimposing a network onto a chip introduces additional factors, such as network latency, routing, and buffer depths all begin to affect the behavior of the system. Communication between processing elements becomes the bottleneck. Current scheduling and orchestration solutions address these issues, but leave room for improvement. In this paper, application profiling is proposed to increase the performance of a NoC’s scheduler; a custom simulator is created to validate this advanced scheduler.